The present invention generally relates to the application of a testing data to a device for testing the device.
In most applications, integrated circuits (IC's) or other electronic devices are tested after production and before use. FIG. 1 shows a schematic diagram of a typical testing unit 10. The testing unit 10 comprises a tester 20 and a device under test (DUT) 30, which can be an IC or any other electronic device. The tester 20 comprises a signal generating unit 40, a signal receiving unit 50, and a signal analyzing unit 60.
The DUT 30 receives a DUT input signal on a line 70 from the signal generating unit 40 of the tester 20, processes those signals, and generates a DUT output signal, which again, is received by the signal receiving unit 50 of the tester 20 via a line 80. The signal analyzing unit 60 receives the DUT input signal, or a corresponding signal derived therefrom, on a line 90 from the signal generating unit 40, and the DUT output signal, or a corresponding signal derived therefrom, on a line 95 from the signal receiving unit 50. The signal analyzing unit 60 analyses those signals, e.g. by comparing the signals. The tester 20 can thus draw conclusions about the properties and quality of the DUT 30.
It is to be understood that for the sake of simplicity, the term `line` as used herein refers to any kind of physical connection. In several applications, the line will be implemented by more or less complex data busses.
The DUT input signal and the DUT output signal are also called vector data and comprise one or more single individual vectors. Each individual vector represents a signal state which is either to be applied at the input of the DUT 30 or output by the DUT 30 at a given point in time.
There are several testing methods known in the art to apply test data to the DUT 30. In a so called `parallel test`, the DUT input data is applied at the inputs of the DUT 30 and the outputs thereof are observed. During a SCAN test, states internal of the DUT 30 can be changed or monitored directly. DUTs 30 that allow SCAN test need special storage devices which can be written in a serial fashion. They can also be read serially. These special storage devices need more silicon area than normal storage devices (flip-flops). In order to reduce the additionally required area boundary SCAN is often implemented. Boundary SCAN devices only have writeable flip-flops at the inputs and outputs of the device, Boundary SCAN test is often used during a board test to directly change and monitor certain states at the boundaries of the DUTs 30 on a board.
In several applications, the signal analyzing unit 60 receives an expected DUT output signal from the signal generating unit 40 and compares that signal with the actual DUT output signal received by the signal receiving unit 50. The expected DUT output signal represents the signal which is expected as DUT output signal in case the DUT 30 is working in the expected way. During the testing, the actually received DUT output signal is compared, e.g. continuously, with the expected DUT output signal. If the signals do not match, the DUT has a functional failure and the test fails.
FIG. 2 shows a typical circuit for the generation of the DUT input signal as known in the art. The DUT input signal is generated under control of a vector processor 100. Similar to the processing of a program by a microprocessor, the vector processor 100 processes a sequence of commands, whereby on demand, data stored in a vector memory 110 can be fetched via a line 120 and might needs to be suitably formatted. Eventually, the DUT input signal is applied on line 70 to the DUT 30. The DUT input signal, or a signal derived therefrom comprising or representing the expected DUT output signals, is also applied on line 90.
The vector memory 110 stores vector data comprising one or more vector sequences which can be any kind of data to be applied to the DUT 30. In most cases, the vector memory 110 is implemented by a semiconductor memory, such as a random access memory (RAM), allowing to flexibly and quickly change the contents thereof. The vector data is stored in the vector memory 110 at defined addresses. When the vector processor 100 applies a respective address word on line 120 to the vector memory 110, vector data corresponding to that address will be available at an output of the vector memory 110 on line 120. This output vector data is further processed by the vector processor 100 and might serve as DUT input signal--or as expected DUT output signal--for testing the DUT 30.
The price of testers 20 strongly depends on the size of the needed memory for storing the testing data for the DUT 30. Particularly when expensive semiconductor memory is employed, it is highly desirable to reduce the memory size needed.
It is known in the art that the size of the vector memory 110 can be reduced by implementing suitable commands or instructions for the vector processor 100. It is made use of the fact that a stream of vector data for testing the DUT 30 might comprise one or more sequences of identical data. Each sequence of identical data is stored separately into the vector memory 110 and can be called up on demand by applying suitable commands. The effective size of the vector memory 110 can thus be reduced corresponding to the frequency of repeated sequences of identical data.
However, it has been found that this way to reduce the required size of the vector memory 110 also involves several disadvantages:
1. Storing of the suitable commands or instructions also requires a certain amount of memory area. PA1 3. Also in case that several instructions reserve the physically identical part of the vector memory 110, instructions and vector sequences use the same memory and thus also have to use the same line, bus or data path. Therefore, instructions and vector sequences cannot be read (reading vector sequences from the memory by the vector processor 100 is generally called vector generation) from the memory at the same time and new vector data cannot be generated while a new instruction is read. This causes interruptions in the vector data stream which have to be avoided because the DUT 30 might behave differently, if the vector stream stops. A stop in the vector stream might cause temperature effects. In some cases (e.g., Phase Locked Loops--PLL--circuits, dynamic logic), the current state of the DUT 30 might be changed so that the DUT 30 might alter its states during the stop. PA1 4. In case that instructions occupy another physical memory, additional costs arise for the additional memory. PA1 5. A certain amount of repeated data sequences is required to achieve a significant improvement of the memory size.
2. In case that several instructions reserve the physically identical part of the vector memory 110, the number of vector sequences storable into the vector memory 110 is limited by the number of instructions.